1. Field of the Invention
The present invention generally relates to techniques for producing high-speed data processing elements and, more particularly, the present invention relates to techniques for producing multi-stage datapath elements with selectively-inserted pipelining stages.
2. State of the Art
Logical data processing elements, such as inverters, typically operate on each bit in a datapath individually. In such elements, an operation on one bit has little, if any, effect on operations on another bit in the datapath. However, with high-speed arithmetic units, such as multipliers, an operation on one bit in a datapath is often dependent upon the results from processing other bits. For instance, in binary multipliers, a carry bit is often generated during an operation on a lower order bit and, then, the carry bit is used in an operation on a higher order bit in the multiplier.
To provide high frequency operation of arithmetic functional units, so-called pipelining stages can be inserted in the units. Although pipelining stages in arithmetic elements have numerous advantages, they also can increase latency times (the period of time required to completely process a word). In other words, because pipelining stages add additional processing steps to arithmetic elements, the elements require longer periods of time to process each individual word. Nevertheless, an arithmetic element's output frequency (i.e., the number of words processed per unit time) may be increased, despite increased latency, by the insertion of pipelining stages in the element. This result follows from the fact that pipelining stages permit an element to begin operating on the next word before the element completes processing of a previous word. Accordingly, although pipelining stages increase element latency times, they also increase the frequency of operation of arithmetic elements.
Thus, the use of pipelining stages necessitates making performance trade-offs between frequency and latency. To achieve optimal or near optimal performance, it is desirable to insert only the minimum number of pipeline stages needed to achieve a desired operating frequency. Stated somewhat differently, pipeline stages ordinarily should be inserted at maximal distances into a functional element.
For practical purposes, the operating frequency of a particular datapath element often is controlled by adjacent functional elements. Accordingly, when an arithmetic element is designed for compatibility with other elements in an existing datapath, any pipeline stages placed in the newly designed element should be located at optimal positions given the other elements in the datapath and given the required operating frequency of the newly designed element.